Invention Grant
- Patent Title: Nanoscale interconnect array for stacked dies
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Application No.: US16378921Application Date: 2019-04-09
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Publication No.: US10600761B2Publication Date: 2020-03-24
- Inventor: Liang Wang , Bongsub Lee , Belgacem Haba , Sangil Lee
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L25/00
Abstract:
A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.
Public/Granted literature
- US20190237437A1 NANOSCALE INTERCONNECT ARRAY FOR STACKED DIES Public/Granted day:2019-08-01
Information query
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