Invention Grant
- Patent Title: Methods of incorporating leaker devices into capacitor configurations to reduce cell disturb
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Application No.: US15843278Application Date: 2017-12-15
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Publication No.: US10650978B2Publication Date: 2020-05-12
- Inventor: Ashonita A. Chavan , Beth R. Cook , Manuj Nahar , Durai Vishak Nirmal Ramaswamy
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01G4/38
- IPC: H01G4/38 ; H01L27/11507 ; G11C11/22 ; H01L49/02

Abstract:
Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.
Public/Granted literature
- US20190189357A1 Methods of Incorporating Leaker Devices into Capacitor Configurations to Reduce Cell Disturb Public/Granted day:2019-06-20
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