Invention Grant
- Patent Title: 3D semiconductor device and structure
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Application No.: US16115519Application Date: 2018-08-28
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Publication No.: US10651054B2Publication Date: 2020-05-12
- Inventor: Zvi Or-Bach , Brian Cronquist , Deepak Sekar
- Applicant: Monolithic 3D Inc.
- Applicant Address: US CA San Jose
- Assignee: MONOLITHIC 3D INC.
- Current Assignee: MONOLITHIC 3D INC.
- Current Assignee Address: US CA San Jose
- Agency: Tran & Associates
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/498 ; H01L27/092 ; H01L23/34 ; H01L27/02 ; H01L21/8234 ; H01L27/06 ; H01L25/065 ; H01L23/60 ; H01L23/522 ; H01L23/367 ; H01L25/00 ; H01L27/098 ; H01L23/373 ; H01L23/50 ; H01L21/8238

Abstract:
A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes a Phase Lock Loop (“PLL”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.
Public/Granted literature
- US20190019693A1 3D SEMICONDUCTOR DEVICE AND STRUCTURE Public/Granted day:2019-01-17
Information query
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