Invention Grant
- Patent Title: White-box implementations with garbled circuits
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Application No.: US15617940Application Date: 2017-06-08
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Publication No.: US10652011B2Publication Date: 2020-05-12
- Inventor: Joppe Willem Bos , Jan Hoogerbrugge , Marc Joye , Wilhelmus Petrus Adrianus Johannus Michiels
- Applicant: NXP B.V.
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Main IPC: G06F21/00
- IPC: G06F21/00 ; H04L9/06 ; H04L9/30 ; G09C1/00 ; G06F21/60

Abstract:
A method for producing a white-box implementation of a cryptographic function using garbled circuits, including: producing, by a first party, a logic circuit implementing the cryptographic function using a plurality of logic gates and a plurality of wires; garbling the produced logic circuit, by the first party, including garbling the plurality of logic gates and assigning two garbled values for each of the plurality of wires; and providing a second party the garbled logic circuit and a first garbled circuit input value.
Public/Granted literature
- US20180359082A1 WHITE-BOX IMPLEMENTATIONS WITH GARBLED CIRCUITS Public/Granted day:2018-12-13
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