Invention Grant
- Patent Title: Method for producing low-permittivity spacers
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Application No.: US15390077Application Date: 2016-12-23
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Publication No.: US10658197B2Publication Date: 2020-05-19
- Inventor: Nicolas Posseme , Maxime Garcia-Barros , Yves Morand
- Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , STMICROELECTRONICS SA , STMICROELECTRONICS (CROLLES 2) SAS
- Applicant Address: FR Paris FR Montrouge FR Crolles
- Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES,STMICROELECTRONICS SA,STMICROELECTRONICS (CROLLES 2) SAS
- Current Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES,STMICROELECTRONICS SA,STMICROELECTRONICS (CROLLES 2) SAS
- Current Assignee Address: FR Paris FR Montrouge FR Crolles
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@42f65366
- Main IPC: H01L21/324
- IPC: H01L21/324 ; H01L21/3115 ; H01L21/02 ; H01L21/223 ; H01L21/322 ; H01L21/447 ; H01L21/762 ; H01L21/8234 ; H01L29/66 ; H01L29/49 ; H01L29/78
Abstract:
There is provided a method for manufacturing a transistor from a stack including at least one gate pattern comprising at least one flank, the method including forming at least one gate spacer over at least the flank of the gate pattern; and reducing, after a step of exposure of the stack to a temperature greater than or equal to 600° C., of a dielectric permittivity of the at least one gate spacer, the reducing including at least one ion implantation in a portion at least of a thickness of the at least one gate spacer.
Public/Granted literature
- US20170186623A1 METHOD FOR PRODUCING LOW-PERMITTIVITY SPACERS Public/Granted day:2017-06-29
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