Invention Grant
- Patent Title: Methods for fabricating finFET devices having gate spacers on field insulating layers
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Application No.: US16170842Application Date: 2018-10-25
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Publication No.: US10658249B2Publication Date: 2020-05-19
- Inventor: Gun Ho Jo , Dae Joung Kim , Jae Mun Kim , Moon Han Park , Tae Ho Cha , Jae Jong Han
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@2c346601
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/66 ; H01L21/02 ; H01L29/786 ; H01L29/78 ; H01L29/423 ; H01L21/84 ; H01L21/8234

Abstract:
A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.
Public/Granted literature
- US20190148521A1 SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME Public/Granted day:2019-05-16
Information query
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