Invention Grant
- Patent Title: Method for converting a floating gate non-volatile memory cell to a read-only memory cell and circuit structure thereof
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Application No.: US15908575Application Date: 2018-02-28
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Publication No.: US10658364B2Publication Date: 2020-05-19
- Inventor: Fabio De Santis , Vikas Rana
- Applicant: STMICROELECTRONICS INTERNATIONAL N.V. , STMICROELECTRONICS S.R.L.
- Applicant Address: IT Agrate Brianza NL Schiphol
- Assignee: STMICROELECTRONICS S.R.L.,STMICROELECTRONICS INTERNATIONAL N.V.
- Current Assignee: STMICROELECTRONICS S.R.L.,STMICROELECTRONICS INTERNATIONAL N.V.
- Current Assignee Address: IT Agrate Brianza NL Schiphol
- Agency: Seed Intellectual Property Law Group LLP
- Main IPC: H01L27/105
- IPC: H01L27/105 ; H01L27/11521 ; G11C29/00 ; H01L27/112 ; H01L27/11519 ; H01L27/11558 ; G11C16/04 ; H01L21/66

Abstract:
According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.
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Information query
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