A memory device may include an array of memory cells having a first area and configured to operate at a first voltage, and circuitry having a second area that at least partially overlaps the first area. The circuitry may be configured to operate at a second voltage lower than the first voltage. The circuitry maybe be further configured to access the array of memory cells using decoder circuitry configured to operate at the first voltage. The array of memory cells and the circuitry may be on a single substrate. The circuitry may include microcontroller circuitry, cryptographic controller circuitry, and/or memory controller circuitry. The memory cells may be self-selecting memory cells that each include a storage and selector element having a chalcogenide material. The memory cells may not include separate cell selector circuitry.