• Patent Title: Method for fabricating a strained semiconductor-on-insulator substrate
  • Application No.: US16301260
    Application Date: 2017-05-17
  • Publication No.: US10672646B2
    Publication Date: 2020-06-02
  • Inventor: Walter SchwarzenbachGuillaume ChabanneNicolas Daval
  • Applicant: Soitec
  • Applicant Address: FR Bernin
  • Assignee: Soitec
  • Current Assignee: Soitec
  • Current Assignee Address: FR Bernin
  • Agency: TraskBritt
  • Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@22327a93
  • International Application: PCT/EP2017/061792 WO 20170517
  • International Announcement: WO2017/198686 WO 20171123
  • Main IPC: H01L27/12
  • IPC: H01L27/12 H01L21/762
Method for fabricating a strained semiconductor-on-insulator substrate
Abstract:
A method for fabricating a strained semiconductor-on-insulator substrate includes bonding a donor substrate to a receiving substrate, with a dielectric layer at the interface, and transferring a monocrystalline semiconductor layer from the donor substrate to the receiving substrate. A portion is cut from a stack formed from the transferred monocrystalline semiconductor layer from the dielectric layer and from the strained semiconductor material layer. The cutting results in the relaxation of the strain in the strained semiconductor material, and in the application of at least a part of the strain to the transferred monocrystalline semiconductor layer. The method also involves the formation, on the strained semiconductor material layer of the receiving substrate, of a dielectric bonding layer or of a bonding layer consisting of the same relaxed, or at least partially relaxed, monocrystalline material as the monocrystalline semiconductor layer of the donor substrate.
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