Invention Grant
- Patent Title: Coherence flows for dual-processing pipelines
-
Application No.: US16124713Application Date: 2018-09-07
-
Publication No.: US10678691B2Publication Date: 2020-06-09
- Inventor: Harshavardhan Kaushikkar , Srinivasa Rangan Sridharan , Xiaoming Wang
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Kowert Hood Munyon Rankin and Goetzel PC
- Agent Rory D. Rankin
- Main IPC: G06F12/0855
- IPC: G06F12/0855

Abstract:
Systems, apparatuses, and methods for implementing coherence flows for dual-processing coherence and memory cache pipelines are disclosed. A dual-processing pipeline includes a coherence processing pipeline and a memory cache processing pipeline. When a transaction is issued to the dual-processing pipeline, the coherence processing pipeline performs a duplicate tag lookup in parallel with the memory cache processing pipeline performing a memory cache tag lookup for the transaction. If the duplicate tag lookup is a hit, then the coherence processing pipeline locks the matching entry, the memory cache processing pipeline discards the original transaction, and a copyback request is sent to a coherent agent identified by the matching entry. When the copyback response is received by a communication fabric, the copyback response is issued to the memory cache processing pipeline. When the copyback response passes the global ordering point, the coherence processing pipeline clears the lock on the matching entry.
Public/Granted literature
- US20200081840A1 COHERENCE FLOWS FOR DUAL-PROCESSING PIPELINES Public/Granted day:2020-03-12
Information query
IPC分类: