Invention Grant
- Patent Title: Method of manufacturing multi-chip package
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Application No.: US16193318Application Date: 2018-11-16
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Publication No.: US10679972B2Publication Date: 2020-06-09
- Inventor: Won-Gil Han , Byong-Joo Kim , Yong-Je Lee , Jae-Heung Lee , Seung-Weon Ha
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Lee IP Law, P.C.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@c21a9ba
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L25/00

Abstract:
A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.
Public/Granted literature
- US20190103381A1 METHOD OF MANUFACTURING MULTI-CHIP PACKAGE Public/Granted day:2019-04-04
Information query
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