Invention Grant
- Patent Title: Digital phase locked loop frequency estimation
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Application No.: US16170716Application Date: 2018-10-25
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Publication No.: US10680619B2Publication Date: 2020-06-09
- Inventor: Elan Banin , Roy Amel , Ran Shimon , Ashoke Ravi , Nati Dinur
- Applicant: Intel IP Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel IP Corporation
- Current Assignee: Intel IP Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schiff Hardin LLP
- Main IPC: H03L7/08
- IPC: H03L7/08 ; H04L27/00 ; H03L7/085 ; H03L9/00

Abstract:
A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a controlled oscillator signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.
Public/Granted literature
- US20190068200A1 DIGITAL PHASE LOCKED LOOP FREQUENCY ESTIMATION Public/Granted day:2019-02-28
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