Invention Grant
- Patent Title: Power bus voltage drop compensation using sampled bus resistance determination
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Application No.: US15179521Application Date: 2016-06-10
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Publication No.: US10700599B2Publication Date: 2020-06-30
- Inventor: Patrizio Vinciarelli
- Applicant: VLT, INC.
- Applicant Address: US CA Sunnyvale
- Assignee: VLT, Inc.
- Current Assignee: VLT, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Foley & Lardner LLP
- Main IPC: H02M3/00
- IPC: H02M3/00 ; H02M1/00

Abstract:
A power system includes a power conversion stage that receives power from an input source and delivers power to a load via a power distribution bus. A control system samples the voltage delivered by the power conversion stage at a location close to the output of the power conversion stage and the load voltage at a location close to the load. The control system further measures the current flowing between the output and the load through the power bus. The samples may be used to determine a representation of the bus resistance. The determined bus resistance may be used to introduce a negative resistance characteristic in the power conversion stage as a way of compensating for the actual bus resistance.
Public/Granted literature
- US20170358978A1 POWER BUS VOLTAGE DROP COMPENSATION USING SAMPLED BUS RESISTANCE DETERMINATION Public/Granted day:2017-12-14
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