Invention Grant
- Patent Title: Dedupe DRAM cache
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Application No.: US15934940Application Date: 2018-03-23
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Publication No.: US10705969B2Publication Date: 2020-07-07
- Inventor: Mu Tien Chang , Andrew Chang , Dongyan Jiang , Hongzhong Zheng
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR
- Agency: Renaissance IP Law Group LLP
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F12/0891 ; G06F3/06

Abstract:
A dedupable cache is disclosed. The dedupable cache may include cache memory including both a dedupable read cache and a non-dedupable write buffer. The dedupable cache may also include a deduplication engine to manage reads from and writes to the dedupable read cache, and may return a write status signal indicating whether a write to the dedupable read cache was successful or not. The dedupable cache may also include a cache controller, which may include: a cache hit/miss check to determine whether an address in a request may be found in the dedupable read cache; a hit block to manage data accesses when the requested data may be found in the dedupable read cache; a miss block to manage data accesses when the requested data is not found in the dedupable read cache; and a history storage to store information about accesses to the data in the dedupable read cache.
Public/Granted literature
- US20190227941A1 DEDUPE DRAM CACHE Public/Granted day:2019-07-25
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