A method includes forming in sequence a metallic capping layer and a dummy gate electrode layer over a semiconductor substrate; patterning the metallic capping layer and the dummy gate electrode layer to form a first stacked structure including a first portion of the metallic capping layer and a first portion of the dummy gate electrode layer; forming a plurality of first gate spacers on opposite sides of the first stacked structure; removing the first portion of the dummy gate electrode layer to expose the first portion of the metallic capping layer; and forming a first work function metal layer on the first portion of the metallic capping layer.