A display device includes a display panel, a voltage generator configured to generate a gate driving voltage, a timing controller configured to generate a clock control signal, a gate controller configured to generate gate clock signals, a gate driver configured to generate a gate signal, an over current protection circuit configured to generate a gate clock current corresponding to the gate clock signals and output a shutdown control signal, and an abnormal signal detector configured to determine whether the clock control signal is abnormal based on a difference of a set reference signal and the clock control signal, and output a delay control signal that delays an output timing of the shutdown control signal from the over current protection circuit for a set time when the clock control signal is abnormal.