A device includes an integrated circuit including a single standard cell that is selected from a standard cell library used for design of the layout of the integrated circuit. The single standard cell includes a first active region, a second active region, a first gate, a second gate, and a third gate. The first gate is arranged over the first active region, for formation of at least one first electrostatic discharge (ESD) protection component. The second gate is separate from the first gate, and the second gate is arranged over the second active region, for formation of at least one second ESD protection component. The third gate is separate from the first gate and the second gate, and the third gate is arranged over the first active region and the second active region, for formation of at least one transistor.