Architectures and layouts for an array of resistive random access memory cells and read and write methods thereof
Abstract:
Various architectures and layouts for an array of resistive random access memory (RRAM) cells are disclosed. The RRAM cells are organized into rows and columns, with each cell comprising a top electrode, a bottom electrode, and a switching layer. Circuitry is included for improving the reading and writing of the array, including the addition of a plurality of columns of dummy RRAM cells in the array used as a ground source, connecting source lines to multiple pairs of rows of RRAM cells, and the addition of rows of isolation transistors.
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