Invention Grant
- Patent Title: Impedance mismatch mitigation scheme that applies asymmetric voltage pulses to compensate for asymmetries from applying symmetric voltage pulses
-
Application No.: US16233780Application Date: 2018-12-27
-
Publication No.: US10755788B2Publication Date: 2020-08-25
- Inventor: Peter Rabkin , Kwang-Ho Kim , Masaaki Higashitani , Yingda Dong
- Applicant: SanDisk Technologies LLC
- Applicant Address: US TX Addison
- Assignee: SanDisk Technologies LLC
- Current Assignee: SanDisk Technologies LLC
- Current Assignee Address: US TX Addison
- Agency: Vierra Magen Marcus LLP
- Main IPC: G11C16/14
- IPC: G11C16/14 ; G11C16/04 ; G11C16/34 ; H01L27/1157 ; H01L27/11524

Abstract:
An apparatus comprising an impedance compensation circuit is disclosed. The impedance compensation circuit compensates for impedance differences between a first pathway connected to a first transistor and a second pathway connected to a second transistor. However, rather than making a compensation based on a signal (e.g., voltage) applied to either the first or the second pathway, a compensation is made based on the signals (e.g., voltage pulses) applied to third and fourth pathways connected to the transistors.
Public/Granted literature
- US20200143889A1 IMPEDANCE MISMATCH MITIGATION SCHEME Public/Granted day:2020-05-07
Information query