Invention Grant
- Patent Title: Warpage control of semiconductor die
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Application No.: US16402042Application Date: 2019-05-02
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Publication No.: US10755995B2Publication Date: 2020-08-25
- Inventor: Yun-Ting Wang , Yi-An Lin , Ching-Chuan Chang , Po-Chang Kuo
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L23/31 ; H01L23/00 ; H01L23/29 ; H01L21/02 ; H01L21/56
Abstract:
A method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Then, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Afterwards, a first oxide-based passivation layer is formed over the metal pad. Then, a second oxide-based passivation layer is formed over the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.
Public/Granted literature
- US20200006182A1 WARPAGE CONTROL OF SEMICONDUCTOR DIE Public/Granted day:2020-01-02
Information query
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