Invention Grant
- Patent Title: Integrated circuit with metal gate having dielectric portion over isolation area
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Application No.: US15835810Application Date: 2017-12-08
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Publication No.: US10756085B2Publication Date: 2020-08-25
- Inventor: Ye Lu , Bin Yang , Lixin Ge
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Withrow & Terranova, PLLC
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L27/06 ; H01L21/768 ; H01L21/8238 ; H01L21/762 ; H03K19/0185 ; H01L21/8234 ; G06F30/398 ; H01L27/092

Abstract:
An integrated circuit may include a substrate, a first three-dimensional (3D) transistor formed on a first diffusion region of the substrate, and a second 3D transistor formed on a second diffusion region of the substrate. The first 3D transistor may include a gate that extends from between a source and a drain of the first 3D transistor, across an isolation region of the substrate, to and between a source and a drain of the second 3D transistor. The gate may include a gate metal that has an isolation portion extending over the isolation region of the substrate and a diffusion portion extending over the first and second diffusion regions of the substrate. The isolation portion of the gate metal has a thickness less than a maximum thickness of the diffusion portion of the gate metal.
Public/Granted literature
- US20190181137A1 INTEGRATED CIRCUIT WITH METAL GATE HAVING DIELECTRIC PORTION OVER ISOLATION AREA Public/Granted day:2019-06-13
Information query
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