Invention Grant
- Patent Title: Memory arrays and methods used in forming a memory array
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Application No.: US16200158Application Date: 2018-11-26
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Publication No.: US10756105B2Publication Date: 2020-08-25
- Inventor: Yoshiaki Fukuzumi , M. Jared Barclay , Emilio Camerlenghi , Paolo Tessariol
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L27/11582 ; H01L27/11565 ; H01L21/768 ; H01L21/28

Abstract:
A method used in forming a memory array comprises forming a tier comprising conductor material above a substrate. Sacrificial islands comprising etch-stop material are formed directly above the conductor material of the tier comprising the conductor material. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the sacrificial islands and the tier comprising the conductor material. Etching is conducted through the insulative tiers and the wordline tiers to the etch-stop material of individual of the sacrificial islands to form channel openings that have individual bases comprising the etch-stop material. The sacrificial islands are removed through individual of the channel openings to extend the individual channel openings to the tier comprising the conductor material. Channel material is formed in the extended-channel openings to the tier comprising the conductor material. The channel material is electrically coupled with the conductor material of the tier comprising the conductor material. Structure independent of method is disclosed.
Public/Granted literature
- US20200168622A1 Memory Arrays And Methods Used In Forming A Memory Array Public/Granted day:2020-05-28
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