A gate driving circuit includes a plurality of stages sequentially connected to one another. The plurality of stages each includes an output unit for outputting a first clock signal as a gate output voltage in response to a voltage of a Q node and a voltage of a QB node; a first node controller configured to charge the voltage of the Q node in response to the gate output voltage from a previous stage; a second node controller configured to charge the voltage of the QB node in response to a second clock signal having a different phase from the first clock signal; a first node stabilizer configured to block a leakage current path of the Q node when the second clock signal is not applied; and a second node stabilizer configured to block a leakage current path of the QB node when the second clock signal is not applied.