Invention Grant
- Patent Title: Volatile memory device with 3-D structure including vertical pillars and memory cells vertically stacked one over anoher in multiple levels
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Application No.: US16112133Application Date: 2018-08-24
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Publication No.: US10790008B2Publication Date: 2020-09-29
- Inventor: Yoshihito Koya
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C11/4091
- IPC: G11C11/4091 ; G11C11/4094 ; G11C11/408 ; G11C11/4096 ; G11C11/4076 ; G11C11/404 ; H01L27/108

Abstract:
Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes volatile memory cells located along a pillar that has a length extending in a direction perpendicular to a substrate of a memory device. Each of the volatile memory cells includes a capacitor and at least one transistor. The capacitor includes a capacitor plate. The capacitor plate is either formed from a portion a semiconductor material of the pillar or formed from a conductive material separated from the pillar by a dielectric.
Public/Granted literature
- US20190066762A1 VOLATILE MEMORY DEVICE INCLUDING STACKED MEMORY CELLS Public/Granted day:2019-02-28
Information query
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