Invention Grant
- Patent Title: Stack of layers for protecting against a premature breakdown of interline porous dielectrics within an integrated circuit
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Application No.: US16260394Application Date: 2019-01-29
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Publication No.: US10796992B2Publication Date: 2020-10-06
- Inventor: Christian Rivero , Jean-Philippe Escales
- Applicant: STMicroelectronics (Rousset) SAS
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Agency: Crowe & Dunlevy
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@5972b237
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/532 ; H01L21/768 ; H01L21/311 ; H01L23/31

Abstract:
A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization level of an interconnection part of the integrated circuit. This stack serves to protect the integrated circuit against a breakdown of at least one dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit. Such a breakdown may occur due to electrical conduction assisted by the presence of defects within the at least one dielectric region.
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Information query
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