- 专利标题: Phase to digital converter
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申请号: US16580117申请日: 2019-09-24
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公开(公告)号: US10819355B1公开(公告)日: 2020-10-27
- 发明人: Firas N. Abughazaleh , David Bearden , James Andrew Welker , Huy Nguyen , Venkatarama Mohanareddy Mooraka
- 申请人: NXP USA, Inc.
- 申请人地址: US TX Austin
- 专利权人: NXP USA, Inc.
- 当前专利权人: NXP USA, Inc.
- 当前专利权人地址: US TX Austin
- 主分类号: H03L7/00
- IPC分类号: H03L7/00 ; H03L7/099 ; H03L7/085
摘要:
A phase to digital converter (PDC) generates a digital output that represents a phase difference between first and second clocks. The PDC includes a gated ring oscillator (GRO), which includes N signal delay elements coupled together in a ring via a logic gate, wherein a 1st signal delay element of the ring comprises an input coupled to an output of the logic gate, and wherein a Nth signal delay element of the ring comprises an output coupled to a first input of the logic gate. A convertor is coupled to the GRO and configured to generate low order bits of the digital output based on outputs of the logic gate and the N signal delay elements. A first counter includes an input coupled to an output of one of the N signal delay elements or the logic gate, wherein the first counter is configured to generate a first digital counter value. A second counter includes an input coupled to an output of another one of the N signal delay elements or the logic gate, wherein the second counter is configured to generate a second digital counter value. The PDC generates the digital output signal based on the low order bits and one of the first and second digital counter values.