A 3D semiconductor device and structure, the device including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, where second die includes an array of memory cells, and where the first die includes decoders for the array.