Memory with an error correction circuit includes: a first error correction circuit performing error correction on first partial data to generate first partial write data or first partial read data; and a second error correction circuit performing error correction on second partial data to generate second partial write data or second partial read data. In a write mode, a plurality of sensing drive circuits respectively receive a plurality of first partial write bits of the first partial write data and a plurality of second partial write bits of the second partial write data, and each sensing drive circuit combines the first partial write bits with the corresponding second partial write bits and writes them to corresponding memory cell columns; in a read mode, the sensing driving circuits respectively sense stored data in the memory cell columns to generate a plurality of first partial read data and second partial read data.