Invention Grant
- Patent Title: Shared error detection and correction memory
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Application No.: US16436767Application Date: 2019-06-10
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Publication No.: US10854310B2Publication Date: 2020-12-01
- Inventor: Chiaki Dono , Taihei Shido , Yuki Ebihara
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/38 ; G11C29/36 ; G11C29/44 ; G11C29/12 ; G11C29/48

Abstract:
Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.
Public/Granted literature
- US20190295679A1 SHARED ERROR DETECTION AND CORRECTION MEMORY Public/Granted day:2019-09-26
Information query