Invention Grant
- Patent Title: Vertical packaging for ultrasound-on-a-chip and related methods
-
Application No.: US16401249Application Date: 2019-05-02
-
Publication No.: US10856844B2Publication Date: 2020-12-08
- Inventor: Keith G. Fife , Jianwei Liu
- Applicant: Butterfly Network, Inc.
- Applicant Address: US CT Guilford
- Assignee: Butterfly Network, Inc.
- Current Assignee: Butterfly Network, Inc.
- Current Assignee Address: US CT Guilford
- Agency: Wolf, Greenfield & Sacks, P.C.
- Main IPC: H01L29/84
- IPC: H01L29/84 ; A61B8/00 ; H01L41/293 ; H01L41/113

Abstract:
Vertical packaging configurations for ultrasound chips are described. Vertical packaging may involve use of integrated interconnects other than wires for wire bonding. Examples of such integrated interconnects include edge-contact vias, through silicon vias and conductive pillars. Edge-contact vias are vias defined in a trench formed in the ultrasound chip. Multiple vias may be provided for each trench, thus increasing the density of vias. Such vias enable electric access to the ultrasound transducers. Through silicon vias are formed through the silicon handle and provide access from the bottom surface of the ultrasound chip. Conductive pillars, including copper pillars, are disposed around the perimeter of an ultrasound chip and provide access to the ultrasound transducers from the top surface of the chip. Use of these types of packaging techniques can enable a substantial reduction in the dimensions of an ultrasound device.
Public/Granted literature
- US20190336103A1 VERTICAL PACKAGING FOR ULTRASOUND-ON-A-CHIP AND RELATED METHODS Public/Granted day:2019-11-07
Information query
IPC分类: