Patterns in an integrated circuit may be evaluated, and a semiconductor device may be fabricated based on the evaluation. The evaluation may include a extracting and superimposing first patterns corresponding to design patterns of the same shape from input layout data generated based on inspecting the integrated circuit, generating distribution data of the first patterns based on the superimposed first patterns, determining an evaluation contour of the design patterns based on an evaluation condition and the distribution data, and generating output layout data based on replacing the first patterns with second patterns each having the evaluation contour. Weak points in the integrated circuit may be detected based on the output layout data. The fabricating may include selectively incorporating an integrated circuit into a semiconductor device based on a determination that the integrated circuit includes less than a threshold quantity and/or threshold concentration of weak points.