- 专利标题: Implementing SEU detection method and circuit
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申请号: US16219252申请日: 2018-12-13
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公开(公告)号: US10896081B2公开(公告)日: 2021-01-19
- 发明人: David D. Cadigan , William V. Huott , Anuwat Saetow , Adam J. McPadden
- 申请人: International Business Machines Corporation
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 Daniel M. Yeates
- 主分类号: G06F11/00
- IPC分类号: G06F11/00 ; G06F11/07
摘要:
A method and a circuit for implementing single event upset (SEU) parity detection, and a design structure on which the subject circuit resides are provided. The circuit implements detection of unwanted state changes due to SEUs, noise or other event in a latch having a default state of zero. The latch includes an L1 latch and an L2 latch with the L2 latch having the connected output and is used and monitored for a flip. A pair of series-connected field effect transistors (FETs) is connected between a drive input of a parity control circuit and ground potential. An inverted output of the L1 latch and a true output of the L2 latch is applied to a respective gate of the pair of series-connected FETs.
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