In various implementations, a memory controller for storage class memory can include an address scrambling circuit. The address scrambling circuit can receive an input address for a processor memory transaction, where the input address is associated with a virtual machine identifier. The address scrambling circuit can further determine an address scrambling mapping from the plurality of address scrambling mappings, where the address scrambling mapping includes a first pattern that determines an alternate set of bits for a set of input bits. The address scrambling circuit can further scramble, using the scrambling circuit and the first pattern, a first part of the input address. The address scrambling circuit can further determine a scrambled address using the input address and the scrambled first part of the input address and output the scrambled address.