An apparatus comprises a main processor to execute a main stream of program instructions, two or more checker processors to execute respective checker streams of program instructions in parallel with each other, the checker streams corresponding to different portions of the main stream executed by the main processor, and error detection circuitry to detect an error when a mismatch is detected between an outcome of a given portion of the main stream executed on the main processor and an outcome of the corresponding checker stream executed on one of the plurality of checker processors. This approach enables high performance main processors 4 to be checked for errors with lower circuit area and power consumption overhead than a dual-core lockstep technique.