A method of manufacturing chip package is disclosed. The method includes providing a wafer having a first surface and a second surface, in which the wafer includes conductive bumps disposed on the first surface; thinning the wafer from the second surface toward the first surface; dicing the wafer to form chips, in which each chip has a third surface and a fourth surface, and at least one of the conductive bumps is disposed on the third surface; disposing the chips on a substrate, such that the conductive bumps are disposed between the substrate and the third surface, in which any two adjacent of the chips are spaced apart by a gap ranging from 50 μm to 140 μm; forming an insulating layer filling the gaps and covering the chips; and dicing the insulating layer along each gap to form a plurality of chip packages.