An apparatus has processing circuitry supporting vector load and store instructions. In response to a transaction start event, the processing circuitry executes one or more subsequent instructions speculatively. In response to a transaction end event, the processing circuitry commits speculative results of those instructions. Hazard detection circuitry detects whether an inter-element address hazard occurs between an address for data element J for an earlier vector load instruction and an address for data element K for a later vector store instruction, where K and J are not equal. In response to detecting the inter-element address hazard, the hazard detection circuitry triggers the processing circuitry to abort further processing of the instructions following the transaction start event and to prevent the speculative results being committed. This approach can provide faster performance for vectorised code.