An array board includes a display area having a non-rectangular shape, TFTs disposed in the display area, a plurality of gate lines disposed in the display area and connected to the TFTs, a non-display area surrounding the display area, unit circuits disposed in the non-display area and connected to the gate lines, and a block connection line. The unit circuits are linearly arranged in the non-display area to form circuit blocks. The circuit blocks in the non-display area form a gate circuit portion in which at least two of the circuit blocks are away from each other in an oblique direction with respect to an arrangement direction of the unit circuits. The block connection line extends across the circuit blocks in the non-display area. The block connection line is connected to the circuit blocks.