A thin film transistor substrate that includes a substrate, a lower gate electrode arranged on the substrate, a semiconductor layer arranged on the substrate and overlapping the lower gate electrode, the semiconductor layer including a channel region interposed between a source region and a drain region, and an upper gate electrode arranged on the substrate and overlapping the semiconductor layer, the upper gate electrode being arranged on an opposite side of the semiconductor layer than the lower gate electrode, wherein at least one of the lower gate electrode and the upper gate electrode is perforated by an aperture to reduce a parasitic capacitance between the upper and lower gate electrodes.