Invention Grant
- Patent Title: Single event latch-up (SEL) mitigation detect and mitigation
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Application No.: US16136104Application Date: 2018-09-19
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Publication No.: US10958067B2Publication Date: 2021-03-23
- Inventor: Pierre Maillard , Yanran Chen , Michael J. Hart
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: H02H9/04
- IPC: H02H9/04 ; H03K17/693 ; H02H5/00

Abstract:
An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contact pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.
Public/Granted literature
- US20200091713A1 SINGLE EVENT LATCH-UP (SEL) MITIGATION DETECT AND MITIGATION Public/Granted day:2020-03-19
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