Shift register includes input sub-circuit coupling input terminal to first node responsive to signal of first clock terminal in input stage, control sub-circuit transmitting signal of second clock terminal to intermediate output terminal according to level at first node and controlling potential of third node according to potential of intermediate output terminal and signal of third clock terminal in input, output and reset stages, pull-up sub-circuit coupling second level terminal to final output terminal responsive to potential of intermediate output terminal in output stage, first voltage stabilization sub-circuit stabilizing voltage between final output terminal and third node responsive to signal of next-stage node connection terminal, pull-down transistor having gate electrode coupled to third node, first electrode coupled to first level terminal, and second electrode coupled to final output terminal. First voltage stabilization sub-circuit lowers potential of third node to level lower than signal of first level terminal in reset stage.