Hot swap inrush current limiter circuit
Abstract:
In one embodiment, a hot swap inrush current limiter circuit includes a pair of paths connecting an input and a load, a first capacitor connected in series with a switch between the paths, a first resistor connected to one of the paths and to a junction between the switch and the first capacitor, a second capacitor connected in series with a second resistor between the paths, with a gate of the switch connected to a junction between the second capacitor and the second resistor, a first diode connected in parallel with the second capacitor, and a second diode connected in parallel with the second resistor to allow for discharge of the second capacitor when input power is off. A method is also disclosed herein.
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