Disclosed herein is an apparatus that includes a first semiconductor chip having a latency counter supplied with a first command and configured to generate a second command when a predetermined period is elapsed after the first command is activated; and a second semiconductor chip having an active control circuit configured to activate a state signal in response to the first command when the state signal is in an inactive state, deactivate the state signal in response to the first command when the state signal is in an active state, and activate the state signal in response to the second command generated based on the first command that is activated when the state signal is in the active state.