Invention Grant
- Patent Title: Ordering updates for nonvolatile memory accesses
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Application No.: US16453784Application Date: 2019-06-26
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Publication No.: US10997064B2Publication Date: 2021-05-04
- Inventor: Sanketh Nalli , Haris Volos , Kimberly Keeton
- Applicant: Hewlett Packard Enterprise Development LP
- Applicant Address: US TX Houston
- Assignee: Hewlett Packard Enterprise Development LP
- Current Assignee: Hewlett Packard Enterprise Development LP
- Current Assignee Address: US TX Houston
- Agency: Sheppard Mullin Richter & Hampton LLP
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G06F12/0804 ; G06F12/0868

Abstract:
Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.
Public/Granted literature
- US20190317891A1 ORDERING UPDATES FOR NONVOLATILE MEMORY ACCESSES Public/Granted day:2019-10-17
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