A display device includes a display panel including a plurality of pixels, a timing controller that generates a first reference clock signal having a first pulse and a second reference clock signal having a second pulse, a signal generator that generates a vertical start signal of which an activation period starts in response to the first pulse and the second pulse and generates a gate clock signal and an inverted gate clock signal based on the first pulse and the second pulse, and a gate driver that generates a gate signal based on the vertical start signal, the gate clock signal, and the inverted gate clock signal and provides the gate signal to the pixels.