A semiconductor memory device includes lower electrodes, each of the lower electrodes surrounding an inner space, an upper support layer on top surfaces of the lower electrodes, the upper support layer being on the inner spaces surrounded by the lower electrodes, and an upper electrode on the upper support layer, the upper electrode filling first and second regions, the second region penetrating the upper support layer, and the first region extending from the second region into between the lower electrodes. Each of the lower electrodes includes a first portion overlapping with the first region, a top surface of the first portion being exposed by the upper support layer, and a second portion covered by the upper support layer, a top surface of the second portion being in contact with the upper support layer.