A SerDes system is provided. The SerDes system includes channel circuits, a PLL circuit, first and second buffers, and first and second capacitors. Each channel circuit is coupled to the first and second clock lines. The PLL circuit generates a first differential signal including first and second clock signals. The first buffer buffers the first clock signal. The second buffer and buffers the second clock signal. The first capacitor receives the buffered first clock signal and outputs a third clock signal to the first clock line. The second capacitor receives a buffered second clock signal and outputs a fourth clock signal to the second clock line. A swing of a second differential signal comprising the third clock signal and the fourth clock signal is smaller than a swing of the first differential signal.