A controller comprises an error correction circuit configured to check an error bit number of error bits in the read data and correct the error bits; a read retry range setting circuit configured to reset a preset read retry range with respect to the read data, and set a new read retry range based on the error bit number and an error correction capability of the error correction circuit; a read voltage setting circuit configured to reset the set read voltage and set, as a new read voltage, a voltage among a plurality of voltages of the reset read retry range, corresponding to the new read retry range; and a flash control circuit configured to control the memory device to perform a read retry operation on the stored data, using the new read voltage.