- 专利标题: Aggregated switch path optimization system
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申请号: US16504086申请日: 2019-07-05
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公开(公告)号: US11012369B2公开(公告)日: 2021-05-18
- 发明人: Karthi Kaliyamoorthy , Senthil Nathan Muthukaruppan
- 申请人: Dell Products L.P.
- 申请人地址: US TX Round Rock
- 专利权人: Dell Products L.P.
- 当前专利权人: Dell Products L.P.
- 当前专利权人地址: US TX Round Rock
- 代理机构: Haynes and Boone, LLP
- 主分类号: H04L12/911
- IPC分类号: H04L12/911 ; H04L12/891 ; H04L12/931 ; H04L12/26 ; H04L12/709 ; H04L12/707
摘要:
An aggregated switch path optimization system includes first and second switch devices. An aggregated third switch device is coupled to the first switch device, the second switch device, and an aggregated fourth switch device. The aggregated third switch device forwards those packets from the first switch device via one of: an ICL to the aggregated fourth switch device, and a link to the second switch device. The aggregated third switch device then monitors a usage of the ICL and the availability of the link to the second switch device. In response to the usage of the ICL exceeding a threshold usage level, or an unavailability of the link to the second switch device, the aggregated third switch device transmits a packet redirection message to the first switch device that causes it to redirect packets away from the aggregated third switch device and towards the aggregated fourth switch device.
公开/授权文献
- US20210006504A1 AGGREGATED SWITCH PATH OPTIMIZATION SYSTEM 公开/授权日:2021-01-07
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