- 专利标题: Systems, methods, and apparatuses for last branch record support compatible with binary translation and speculative execution using an architectural bit array and a write bit array
-
申请号: US14752891申请日: 2015-06-27
-
公开(公告)号: US11048516B2公开(公告)日: 2021-06-29
- 发明人: Paul Caprioli , Koichi Yamada , Jason M. Agron , Jiwei Lu
- 申请人: Paul Caprioli , Koichi Yamada , Jason M. Agron , Jiwei Lu
- 申请人地址: US OR Hillsboro; US CA Los Gatos; US CA San Jose; US CA Pleasanton
- 专利权人: Paul Caprioli,Koichi Yamada,Jason M. Agron,Jiwei Lu
- 当前专利权人: Paul Caprioli,Koichi Yamada,Jason M. Agron,Jiwei Lu
- 当前专利权人地址: US OR Hillsboro; US CA Los Gatos; US CA San Jose; US CA Pleasanton
- 代理机构: Nicholson De Vos Webster & Elliott LLP
- 主分类号: G06F9/38
- IPC分类号: G06F9/38 ; G06F9/30
摘要:
Systems, methods, and apparatuses for last branch record support are described. In an embodiment, a hardware processor core comprises a hardware execution unit to execute a branch instruction, at least two last branch record (LBR) registers to store a source and destination information of a branch taken during program execution, wherein an entry in a LBR register is to include an encoding of the branch, a write bit array to indicate which LBR register is architecturally correct, an architectural bit array to indicate when an LBR register has been written, and a plurality of top of stack pointers to indicate which LBR register in a LBR register stack is to be written.
公开/授权文献
信息查询