Invention Grant
- Patent Title: Forming interconnect without gate cut isolation blocking opening formation
-
Application No.: US16517827Application Date: 2019-07-22
-
Publication No.: US11056398B2Publication Date: 2021-07-06
- Inventor: Daniel J. Jaeger , Naved A. Siddiqui , Shimpei Yamaguchi , Shreesh Narasimha
- Applicant: GLOBALFOUNDRIES U.S. Inc.
- Applicant Address: US CA Santa Clara
- Assignee: GLOBALFOUNDRIES U.S. Inc.
- Current Assignee: GLOBALFOUNDRIES U.S. Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Hoffman Warnick LLC
- Agent Francois Pagette
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/768 ; H01L27/088 ; H01L29/66 ; H01L29/78

Abstract:
A method includes forming a gate cut opening by removing a sacrificial material from a portion of a dummy gate in a first dielectric over a substrate. The gate cut opening includes a lower portion in which the sacrificial material was located and an upper portion extending laterally over the first dielectric. Filling the gate cut opening with a second dielectric creates a gate cut isolation. Recessing the second dielectric creates a cap opening in the second dielectric; and filling the cap opening with a third dielectric creates a dielectric cap. The third dielectric is different than the second dielectric, e.g., oxide versus nitride, allowing forming of an interconnect in at least a portion of the third dielectric without the second, harder dielectric acting as an etch stop.
Public/Granted literature
- US20210028067A1 FORMING INTERCONNECT WITHOUT GATE CUT ISOLATION BLOCKING OPENING FORMATION Public/Granted day:2021-01-28
Information query
IPC分类: